1. Field of the Invention
The invention relates to methods and circuits for low power consuming high-voltage level shifting and related circuitry.
2. Description of Related Art Including Information Disclosed under 37 CFR 1.97 and 1.98
Many integrated circuits, such as display drivers, require a combination of high-voltage driving capability (an output voltage swing up to 100V or more) and a digital control using standard 5V CMOS logic. Hence, complex level-shifting circuits are needed to convert the 5V control signals into the desired high-voltage output waveforms. Moreover, in many of those applications, the system is battery-powered and very severe constraints are put on the power consumption of the level-shifters. An application where both high-voltage driving capability and extremely low power consumption are required is the design of driver chips for cholesteric texture LCDs as discussed by J. W. Doane, D. K. Yang and Z. Yaniv in their paper, “Front-lit Flat Panel Display From Polymer Stabilized Cholsteric Textures”, in the proceedings of the 12th International Display Research Conference (Japan 92), p. 73. As discussed in the paper, quite high voltage levels (50V rms) are necessary to switch this kind of liquid crystal from one stable state to another. However, its inherent memory function (images remain unchanged on the screen without the need for continuous refreshing) is a major advantage compared to other types of liquid crystals, as it allows the implementation of certain display systems with very low image frame rates and a high degree of power efficiency. Consequently, these cholesteric texture LCDs are ideal components for use in battery-operated display systems with slowly or sporadically varying images. The cholesteric texture LCD's do, however, require the development of the generation of the required waveforms on the display rows and columns, and high-voltage driver circuits with very low power dissipation.
In most high-voltage CMOS technologies five different kinds of n- and p-type MOS transistors, such as shown in FIGS. 1A-1E, are used. The devices shown in FIG. 1(a) and FIG. 1(b) are standard non-floating NMOS and floating PMOS transistors for normal 5V operation (used in the CMOS control logic). The PMOS device shown in FIG. 1(c) can float up to a high voltage with respect to the substrate potential. However, in the PMOS device of FIG. 1(c) VGS (the voltage between the gate and the source) and VDS (the voltage between the drain and the source) are limited to 5V, and hence this transistor is ideally suited for controlling the gate electrode of the PDMOS transistor in the output stage. It also serves very well as an active load in a voltage mirror. The NDMOS and floating PDMOS MOSFETs shown in FIG. 1(d) and FIG. 1(e) respectively have to withstand a high voltage between their source and drain electrodes (such as the ones in the output stage or the switching transistors in the voltage mirrors).
One basic version of a high-voltage level-shifter is the well-known circuit shown in FIG. 2. This circuit exhibits a classic complementary output stage with independent control of the gate voltages of the NDMOS and PDMOS transistors 30 and 32 respectively. Standard 5V logic is used to control the NDMOS transistor 30, while a voltage mirror made up of transistors 34 and 36 is required to apply the appropriate gate signal to the PDMOS transistor 32. Unfortunately, the gate control of the PDMOS transistor 32 is not optimum, as is demonstrated by HSPICE-simulations represented by the graphs of FIG. 3. These HSPICE-simulations are based on transistor model parameters from a high-voltage extension of a 0.7 μm CMOS technology. When the input data line shown at 38 in FIG. 3(b) is switched from a logical “1” to “0”, the VGS of transistors 36 and 32 is not entirely discharged to 0V but to a value of approximately −1V, being the threshold voltage of the PMOS transistor 36. Consequently, the PDMOS output transistor 32, having a slightly different threshold voltage, is not driven 100% into cut-off operation, resulting in an output voltage of 0.5V instead of the ideal 0V value as shown at 40 in FIG. 3(c). Moreover, the simultaneous conduction of both DMOS transistors 30 and 32 in the output stage represents a significant waste of energy.
The problem can be solved by discharging the VGS of the PDMOS output transistor 32 completely to 0V by means of a current mirror as illustrated in FIG. 4. It should be noted that common components of FIGS. 2 and 4 carry the same reference numbers. On the “1” to “0” transition of the input signal 40, the constant current source 42 providing a current IBIAS and the current mirror transistors 44 and 46 ensure that the VGS of transistors 32 and 34 is pulled down to 0V as shown at 48 in FIG. 5(c), resulting in a satisfactory logical “0” state at the driver output and avoiding the unnecessary power dissipation in the output DMOS transistors. FIG. 5 shows the HSPICE-simulation results on this circuit. An alternative approach to the circuit of FIG. 4 is the level-shifter proposed by M. Declercq and M. Schubert in their paper, “Circuit Intermédiaire Entre Un Circuit Logique à Basse Tension et un étage de Sortie à Haute Tension Réalisés Dans Une Technolgie CMOS Standard”, also identified as patent 92 06030 at the Institut National de la Propriété Industrielle, Paris (France), where the current source 42 is no longer constant but controlled by the inverted input signal, resulting in a balanced circuit configuration. However, the level-shifter of FIG. 4 and all the variations described in the literature, have one major drawback: they show continuous power dissipation in the voltage mirrors for a logical “0” and/or a logical “1” at the data input. In the case of the simulation in FIG. 5(a) for instance, it can be seen that a stationary 150 μA current is flowing flowing through the drain termination of transistor 34 when a logical “1” bit is applied to the data input. This, of course, is unacceptable in battery-powered applications.
When considering cholesteric texture LCD drivers low-power high-voltage CMOS level-shifters cannot be used directly because they have a purely digital output (the output voltage is switched between 0V and VHV supply voltage), while the cholesteric texture LCDs need waveforms which are far more complicated. Some of the driving schemes require three-, four- or even five-level logic, and others need analog multiplexers to select complex analog waveforms. Hence, for all those applications, an analog switch, capable of withstanding high voltages and exhibiting the same extremely low power dissipation as high-voltage level-shifters, is needed. One classic circuit for a high-voltage analog switch is shown in FIG. 6. In this complementary analog switch, two diodes 50 and 52 have been included to avoid the unwanted conduction of the drain-bulk diodes in the DMOS transistors. To obtain the conducting “ON” state of the switch, the source-gate voltages of the DMOS devices should be VGS,N=VGS,P=OV is needed. Although the circuit is widely used in all kinds of applications, it has some important drawbacks: since the gate potential of the PDMOS transistor 54 has to be 5V lower than the VHV analog signal on input 56 to put the switch in the conducting “ON” state and since the gate potential of the NDMOS transistor 58 should exceed the VHV signal with 5V under the same circumstances, the voltage range of the control circuit (responsible for applying the appropriate signals to the gates of the 2 DMOS transistors) should be at least 10V in excess of the total VHV range. For the control of the NDMOS transistor 58, a double voltage mirror is required. The first one shifts the 5V control input signals upwards towards an auxiliary supply voltage that is at least 5V higher than the highest VHV value, and then the second voltage mirror shifts these signals downwards to the VHV level. The choice of the transistor parameters in this double voltage mirror is extremely critical and very special care has to be taken to avoid excessive voltages on the gates of the transistors. Small deviations of the real transistor parameters from the values used in the simulations could result in transistor breakdown. This classic high-voltage analog switch uses a floating NDMOS device, meaning that its bulk can float up to a high voltage with respect to the substrate potential. Unfortunately, in many high-voltage CMOS technologies only non-floating NDMOS transistors (where the substrate acts as the transistor bulk) are available.
In summary it can be stated that no high-voltage level shifting circuit with low power consumption is known to be in the prior art. Indeed in state of the art level shifting circuitry, simultaneous conduction of the output stage transistors or of the circuitry controlling these output stage transistors is typical. This leads to continuous power dissipation. Also conventional analog switch concepts are not suited for high-voltage switching. Such an analog switch will need control circuitry, such as in the level-shifters, suited for high-voltage switching and with low power consumption, which are not available in the state of the art.
Therefore, it is an object of the invention to provide circuitry which can be used in high-voltage level shifting circuits and analog switches which have no continuous power dissipation and no simultaneous conduction of the output stage transistors. The use of such circuitry results in extremely low power consumption in high-voltage level shifters and analog switches. The circuitry enables implementation of dynamic control of the charge on the gate electrodes of the high-voltage output transistor.